Illegal State Space Identification for Sequential Circuit Test Generation, M.H. Konijnenburg, J.Th. van der Linden, and A.J. van de Goor, Proc. of the Design, Automation and Test in Europe Conference, March 9-12, 1999, Munich, Germany.
Complete Search in Test Generation for Industrial Circuits with Improved Bus-conflict Detection, J.Th. van der Linden, M.H. Konijnenburg and A.J. van de Goor, Proc. of The Seventh Asian Test Symposium, December 2-4, 1998, Singapore, pp.212-219.
Sequential Test Generation with Advanced Illegal State Search, M.H. Konijnenburg, J.Th. van der Linden and A.J. van de Goor, Proc. International Test Conference 1997, pp.733-742.
Circuit-Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors, J.Th. van der Linden, M.H. Konijnenburg, A.J. van de Goor, Proc. Asian Test Symposium Nov. 20-22, 1996, Hsinchu, Taiwan, pp.29-33.
Accelerated Compact Test Set Generation for Three-State Circuits, M.H. Konijnenburg, J.Th. van der Linden, A.J. van de Goor, Proc. International Test Conference Oct. 21-26, 1996, Washington D.C., USA, pp.29-38.
Automatic Test Pattern Generation for Industrial Circuits with Restrictors, M.H. Konijnenburg, J.Th. van der Linden, A.J. van de Goor, Microelectronics Journal, Volume 26, No. 7, October 1995, pp. 635-645.
Compact Test Sets for Industrial Circuits, M.H. Konijnenburg, J.Th. van der Linden, A.J. van de Goor, Proc. 13th IEEE VLSI Test Symposium 1995, Princeton, New Jersey; April 1995, pp.358-366.
Partitioning Circuits with Three-State Buses for ATPG, J.Th. van der Linden, M.H. Konijnenburg, A.J. van de Goor, Proc. of the first annual conference of the Advanced School for Computing and Imaging, May 1995, Heijen, The Netherlands; ISBN 90-9008344-8, pp. 109-118.
Parallel Patterns Fast Fault Simulation for Three-State Circuits and Bidirectional I/O, J.Th. van der Linden, M.H. Konijnenburg, A.J. van de Goor, Proc. International Test Conference 1994, Washington D.C., USA; pp.604-613.
Test-Vector Constraints Reduce Program-Generation Efforts, M.H. Konijnenburg, J.Th. van der Linden, A.J. van de Goor, Test & Measurement Europe, July 1994, pp.35-37.
Test Generation and Three-state Elements, Busses, and Bidirectionals, J.Th. van der Linden, M.H. Konijnenburg, A.J. van de Goor, Proc. 12th IEEE VLSI Test Symposium 1994, Cherry Hill, USA; pp.114-121.
Test Generation and Three-State Elements, Busses, and Bidirectionals, J.Th. van der Linden, Proc. of the Eighth Workshop Computer Systems, March 1994, Amsterdam, The Netherlands; University of Amsterdam rep. no NUGI 832, pp. 47-57.
Test Pattern Generation with Restrictors. M.H. Konijnenburg, J.Th. van der Linden and A.J. van de Goor. Proc. International Test Conference 1993, Baltimore, USA; pp.598-605.
Parallel Automatic Test Pattern Generation for Large Digital Circuits Aiming at Small Test Sets, J.Th. van der Linden, Proc. of 5th Workshop on design, realisation and application of Advanced Computersystems, Feb. 1992, Enschede, The Netherlands; ISBN 90-365-0495-3, pp. 1-7, (In Dutch).